FIG. 11 is a schematic diagram showing a data transmission path of an IC testing apparatus conventionally used. In this drawing, reference numeral 1 denotes a host computer, reference numeral 1A denotes a data transmitter section in the host computer 1, and reference numeral 1B denotes a data receiver section. Reference numerals 2-1, 2-2, 2-n each denote a terminal that operates under instructions from the host computer 1. In this example of the IC testing apparatus, the terminal 2-1 may serve as a pattern generator section, the terminal 2-2 may serve as a timing generator section, and the terminal 2-n may serve as a test head, for example.
Each terminal 2-1, 2-2, . . . , 2-n has an input/output interface 3, and the interfaces 3 are connected in series to an outgoing data bus line 4. Data addressed to each terminal 2-1, 2-2, . . . , 2-n transmitted over the outgoing data bus line 4 is taken in by the terminal through the interface 3.
Data to be delivered from each terminal 2-1, 2-2, . . . , 2-n to the host computer 1 is output to the outgoing data bus line 4 from the interface 3. The data is transmitted through an incoming data bus line 5 and received by the data receiver section 1B of the host computer 1 and thus taken in by the host computer 1.